01141nab a22002535a 4500 114166 PUCSP 20191122162218.0 020228s1995 r 000 0 d PUCSP PUCSP Tachibana, Suguru A 2.6pns wave-pipelined CMOS SRAM with dual-sensing-latch circuits Suguru Tachibana Eletricidade Eletrônica Engenharia 0101426 New York v.30, n.4, apr, 1995, p.487-490 IEEE JOURNAL SOLID STATE-CIRCUITS IEEE Journal solid state-circuits : http://pergamum.pucsp.br/acervo/114166 Ver no Pergamum Biblioteca do Centro de Ciencias Exatas 620.005 IEEESSC -2 Nov 22 2019 3:32PM Artigo 620 Engenharia 620 Engenharia Inclusion 114166 A 26PNS WAVE PIPELINED CMOS SRAM WITH DUAL SENSING LATCH CIRCUITS IEEE JOURNAL SOLID STATE CIRCUITS DICIONARIOS ELETRICIDADE ELETRONICA ESTUDO E ENSINO PROBLEMAS QUESTOES EXERCICIOS TACHIBANA SUGURU 2.6pns wave-pipelined CMOS SRAM with dual-sensing-latch circuits, A / 1995 Artigo