Documenti analoghi

• A 6-ns 4-Mb CMOS SRAM with offset-voltage-insensitive current sense amplifiers
  di: Ishibashi, Koichiro
• A souce sensing tecnique applied to SRAM cells
  di: O'Connor, Kevin J
• Precise CMOS current sample/hold circuits using differential clock feedthrough attenuation techniques
  di: Wu, Chung-Yu
• A 0.65-ns, 72-kb ECL-CMOSRAM macro for a 1-Mb SRAM
  di: Nambu, Hiroaki
• A bootstrapped bipolar CMOS (B2-CMOS) gatefor low-voltage applications
  di: Embabi, Sherrif H. K